電機成員

系主任

系主任 Li, Chien-Mo 李建模

  • 國立台灣大學電機工程學系 專任教授
  • 博士 Stanford University, 2002
  • 碩士 Stanford University, 1997
  • 學士 National Taiwan University, 1993
主要研究領域

積體電路測試及診斷

研究領域摘要

Professor Li’s research focuses on VLSI testing and diagnosis, especially for digital circuits. Specifically, Professor Li is working on these topics: Built-In Self Test (BIST), System-on-Chip (SoC) Testing and Diagnosis, Defect Based Testing, Fault Diagnosis.

  1. Automatic Test Pattern Generation
  2. Fault Diagnosis and Yield Improvement
  3. Low Power Testing
  4. Asynchronous Circuit Design and Test
簡傳

Prof. Li is currently an associate professor at the Electrical engineering department and GIEE of National Taiwan University(NTU). He belongs to the EDA group of GIEE. Dr. Li obtained his PhD degree at Stanford University in 2002. He obtained his MSEE degree from Stanford in 1997 and BSEE degree from NTU in 1993.

Prof. Li's research focuses on the test and diagnosis of VLSI circuits. He is currently one of the faculty members of the Lab of Dependable Systems (LaDS), NTU.

Journal articles & book chapters
  1. Tsai-Chieh Chen,·Chia-Cheng Pai,·Yi-Zhan Hsieh,·Hsiao-Yin Tseng,·James Chien-Mo Li,·Tsung-Te Liu,·I-WeiChiu, “Clock-less DFT and BISTfor Dual-rail Asynchronous Circuits,” Journal of Electronic Testing: Theory and Application, 2021
  2. Shih-An Hsieh, Ying-Hsu Wang, Ting-Yu Shen, Kuan-Yen Huang, Chia-Cheng Pai Tsai-Chieh Chen and James Chien-Mo Li, “DR-scan: Dual-rail Asynchronous Scan DfT and ATPG,” IEEE Trans. CAD, 2018
  3. B. Liu, J. C.M. Li,, “PSN-aware Circuit Test Timing Prediction using Machine Learning,” IET Computers & Digital Techniques, vol. 11, no. 2, pp. 60-67, 3 2017., 2017

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Conference & proceeding papers:
  1. Min-Yan Su, Wei-Chen Lin, Yen-Ting Kuo, Chien-Mo Li, Eric Fang,, “Chip Performance Prediction Using Machine Learning Techniques,,” VLSI-DAT , 2021
  2. Hsiao-Yin Tseng, I-Wei Chiu, Mu-Ting Wu, and James Chien-Mo Li,, “Machine Learning-Based Test Pattern Generation for Neuromorphic Chips,,” IEEE ICCAD, 2021

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Patents:
  1. J. Y. Wen and J. C. M. Li, “Method for adjusting clock domain during layout of integrated circuit and associated computer readable medium,” 美國/中華民國專利申請中, 2010
  2. 王偉哲 李建模, “包含未知訊號之測試結果壓縮設計,” 中華民國專利申請中, 2009

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other:
  1. J. C.-M. Li, and M. Hsiao, “Electronic Design Automation,” Morgan Kaufmann, 2009
  2. Wang, Wu, Wen and et. al., “VLSI Test Principles and Architectures,” Morgan Kaufmann, USA, 800 pages, 2006, ISBN:ISBN-10: 0123705975 and ISBN-13: 978-0123705976

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